1. Field of the Invention
The present invention relates to a driving circuit and a driving method for a display device.
2. Description of the Related Art
Flat panel displays (hereinafter referred to as FPDs) such as liquid crystal displays (hereinafter referred to as LCDs), plasma display panels (PDP), electroluminescences (ELs), field emission displays (FEDs) are used for displays such as computer monitors, instead of cathode ray tubes (CRT), which are heavy and consume a large amount of power. These FPDs have a plurality of pixels arranged in a matrix form.
The LCDs are representatives of the FDPs. Active matrix type LCDs, among the LCDs, using thin film transistors (hereinafter referred to TFTs) as switching elements are commonly used.
An LCD includes two panels and a liquid crystal between the two panels. One panel has a plurality of pixel electrodes, switching elements and wirings, and the other panel has a common electrode and color filters. A pixel electrode and a common electrode, along with the liquid crystal between the two electrodes, form a liquid crystal capacitor, and the potential difference between the two electrodes causes the molecules of the liquid crystal to be distorted, thereby rotating the polarization of incident light. A liquid crystal capacitor and a switching element form a pixel of an LCD, but only a pixel electrode and a switching element are often considered as components of a pixel.
Referring to FIG. 1, a conventional active matrix liquid crystal display and its driving circuit are described.
A plurality of pixels (not shown) driven by wirings are formed in a liquid crystal panel 1 into a matrix. The matrix of the pixels are named as the "pixel matrix", and a "pixel row" and a "pixel column" are terms meaning a row of the pixel matrix and a column of the pixel matrix respectively, in this specification and claims. In addition, the pixels of a pixel row and the pixels of a pixel column are defined as the "row pixels" and the "column pixels", respectively.
Examples of the wirings are scanning lines, or gate lines, G.sub.1, G.sub.2, . . . , G.sub.m-1, G.sub.m, G.sub.m+1, . . . , G.sub.M, which transmit scanning signals to the pixels, and image signal lines, or data lines, D.sub.1, D.sub.2, . . . , D.sub.2N, which transmit image signals or image data to the pixels. Each pixel is connected to one of the gate lines G.sub.1, . . . , G.sub.M and one of the data lines D.sub.1, . . . , D.sub.2N, and is driven by the signals from the gate line and the data line. The number of the gate lines G.sub.1, . . . , G.sub.M is equal to that of the pixel rows, and the number of the data lines D.sub.1, . . . , D.sub.2N is the same as that of the pixel columns.
Generally, a pixel of an LCD further includes a storage capacitor having a large capacitance in order to keep data voltages charged in the liquid crystal capacitors. The data voltage is the potential of the pixel electrode with respect to the potential of the common electrode, that is, the potential difference between the two terminals of the liquid crystal capacitor. The storage capacitors are made in two types, a previous gate type and an independent wiring type. In the previous gate type, a terminal of the storage capacitor of a pixel is connected to a pixel electrode of the pixel, while the other terminal is connected to a previous gate line, which is a term meaning a gate line connected to the previous row pixels. The LCD of the previous gate type requires an additional wiring (not shown) called a storage gate line or a zero-th gate line for the first row pixels. The storage gate line is usually formed above the first gate line G.sub.1, and a terminal of the storage capacitor of each first row pixel is connected to the storage gate line. The storage gate line is applied with a scanning signal or a common signal, which is applied to the common electrode. On the other hand, an LCD of the independent wiring type has a plurality of storage electrode lines (not shown) formed between the gate lines, and a terminal of each storage capacitor is connected to the storage electrode lines applied with the common signal.
The gate lines G.sub.1, . . . , G.sub.M are arranged in a transverse direction on the panel 1 and are connected to a gate driver 20. The data lines D.sub.1, . . . , D.sub.2N are longitudinally formed on the panel 1 and are connected to upper and lower data drivers 12 and 14. The data drivers 12 and 14 are positioned at the upper and the lower parts of the panel 1, respectively. The odd data lines D.sub.1, D.sub.3, . . . , D.sub.2N-1 are connected to the lower data driver 14, while the even data lines D.sub.2, D.sub.4, . . . , D.sub.2N connected to the upper data driver 12. The data drivers 12 and 14 are connected to a controller 100.
A conventional driving method of the conventional LCD shown in FIG. 1 is now described.
When input image data from outside enter the controller 100, the controller 100 sends the image data corresponding to the odd column pixels to the lower data driver 14 and those corresponding to the even column pixels to the upper data driver 12.
When a start signal STV is applied to the gate driver 20, the gate driver 20 supplies a scanning signal to the first gate line G.sub.1, thereby turning on switching elements (not shown) connected to the first gate line G.sub.1. Then, the upper data driver 12 and the lower data driver 14 apply the image data to the first row pixels via the data lines D.sub.1, . . . , D.sub.2N.
When the application of the scanning signal for the first gate line G.sub.1 is finished, a scanning signal is applied to the second gate line G.sub.2. Then, since the switching elements of the first row pixels are turned off and the switching elements of the second row pixels are turned on, the image data corresponding to the second row pixels are applied to the second row pixels.
By way of the above described method, the pixel rows are sequentially scanned from the first pixel row to the last pixel row. When the scanning of the last pixel row is completed, that is, scanning for a frame is completed, the scanning signal is applied to the first gate line G.sub.1 again and so the next frame begins.
However, since the more gate lines become required as the resolution of the display becomes higher, while the time required for one frame scanning remains limited, the time for scanning of one pixel row is reduced. Furthermore, as the size of the screen becomes larger, the lengths of the data lines become longer and thus the RC delay becomes larger. Accordingly, the image quality becomes worse.